• R.M.Rehana
• A.Krishna Mohan

With the revolution in integrated circuits, great emphasis was given on performance and miniaturization. Speed, area and power became the main criterion upon which a VLSI system is measured in terms of its efficiency. For high performances of the execution cores in the logic and arithmetic logic unit the efficiency of energy is essential. For highest power density of the processor block is a part of the adder. It creates a thermal hot spots and sharp temperature gradients to operate the system with the circuit which have high performance. The multiple ALUs presence in modern superscalar processors and execution cores of chip further associate with aggravates the problem by impacting circuit reliability. It increases the cooling costs for the purposes of design. Basically the adder circuit is designed to achieve low power and less delay and by logic gate of the circuit improves the performances. For speed process high logic circuit is implemented and also to have less propagation. In hybrid CMOS design style various adder cells and transistor is used, but in proposed circuit Dual Rail Signal System (DRPTL) is implemented with the load condition and the clock signal to manage the power flow in the circuit and the process is performed in an efficient way in terms of its gate count and thereby on power and speed.

Single Rail Signal system, Dual Rail Signal System, Ripple Carry Adder

" Power Efficient CMOS DRPTL Adder Topologies", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.8, Issue 2, page no.1975-1980, February-2021, Available :http://www.jetir.org/papers/JETIR2102239.pdf

" Power Efficient CMOS DRPTL Adder Topologies", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.8, Issue 2, page no. pp1975-1980, February-2021, Available at : http://www.jetir.org/papers/JETIR2102239.pdf