• Shyam Sundar Karma

This paper introduces a new design method for minor delays and Vedic repetitions effectively based on ancient Vedic Mathematics techniques. It is a N × N multiplication technique used and provides very little delay and an effective location for calculating multiplication. The efficiency of Urdhva Tiryagbhyam Vedic method for multiplication which is different from the process of normal multiplication is used. Urdhava Tiryagbhyam is most efficient algorithm is the most efficient algorithm that gives minimum delay for multiplication for all types of numbers irrespective of their size. Vedic multiplier is coded in VHDL which is simulated and synthesized by using Xilinx ISE 14.7. The proposed design is analyzed according to the delay and memory usage.

Vedic Multiplier, Urdhava Tiryagbhyam sutra, high speed, Digital signal processing.

"Design and Implementation of High-Speed Vedic Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.8, Issue 3, page no.47-51, March-2021, Available :http://www.jetir.org/papers/JETIR2103397.pdf

"Design and Implementation of High-Speed Vedic Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.8, Issue 3, page no. pp47-51, March-2021, Available at : http://www.jetir.org/papers/JETIR2103397.pdf