• Nuka Gnana Prasuna
• Srikanth Talari

This paper describes about different low power techniques that have been implemented using Verilog HDL and some of them using schematics also. Different low power techniques are implemented for different designs and they are simulated and synthesized. The designs are simulated and synthesized using Cadence tools. The net lists and power reports after synthesis have been generated by using the RTL compiler tool of CADENCE. The simulation waveforms with and without using the low power techniques for the designs are compared.

Low power, Verilog, Simulation, Synthesis, Power.

"Reducing Power Dissipation in VLSI Circuits Using Low Power Techniques", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.8, Issue 4, page no.185-189, April-2021, Available :http://www.jetir.org/papers/JETIR2104025.pdf

"Reducing Power Dissipation in VLSI Circuits Using Low Power Techniques", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.8, Issue 4, page no. pp185-189, April-2021, Available at : http://www.jetir.org/papers/JETIR2104025.pdf