UGC Approved Journal no 63975(19)

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Published in:

Volume 8 Issue 8
August-2021
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR2108408


Registration ID:
314130

Page Number

d299-d303

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Title

THREE DIMENSIONAL PARITY FORTCAM BASED FPGA FOR ERROR DETECTION AND CORRECTION

Abstract

Abstract - Delicate mistakes are a significant concern for current electronic circuits and, specifically, for recollections. A delicate blunder can change the substance of the pieces put away in a memory and cause a framework disappointment. Ternary content addressable memories (TCAMs) are generally utilized in network gadgets to execute bundle characterization. They are utilized, for instance, for bundle sending.TCAMs are commonly implemented as standalone devices or as an intellectual property block that is integrated on networking application-specific integrated circuits. On the other hand, field-programmable gate arrays (FPGAs) do not include TCAM blocks. In any case, the adaptability of FPGAs makes them appealing for SDN executions, and most FPGA sellers give improvement packs to SDN. Those need to help TCAM usefulness and, hence, there is a need to imitate TCAMs utilizing the rationale blocks accessible in the FPGA. As of late, various plans to imitate TCAMs on FPGAs have been proposed. Some of them take advantage of the large number of memory blocks available inside modern FPGAs to use them to implement TCAMs. The recollections can be secured with an equality check to identify mistakes or with a blunder revision code to address them, yet this requires extra memory bits per word. For detecting MBUs in the configuration frames of the FPGA, we propose a technique, namely, interleaved n dimensional (InD) parity. Furthermore, by carefully dividing the frames into several clusters, the proposed technique can detect and correct an MBU affecting several adjacent configuration frames.

Key Words

Index Terms – Field-programmable gate arrays (FPGA),soft errors, ternary content addressable memories (TCAM).

Cite This Article

"THREE DIMENSIONAL PARITY FORTCAM BASED FPGA FOR ERROR DETECTION AND CORRECTION", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.8, Issue 8, page no.d299-d303, August-2021, Available :http://www.jetir.org/papers/JETIR2108408.pdf

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2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"THREE DIMENSIONAL PARITY FORTCAM BASED FPGA FOR ERROR DETECTION AND CORRECTION", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.8, Issue 8, page no. ppd299-d303, August-2021, Available at : http://www.jetir.org/papers/JETIR2108408.pdf

Publication Details

Published Paper ID: JETIR2108408
Registration ID: 314130
Published In: Volume 8 | Issue 8 | Year August-2021
DOI (Digital Object Identifier):
Page No: d299-d303
Country: Coimbatore / Coimbatore, Tamilnadu, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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