• Sk. Ayesha
• Dr. Mohammad Hayath Rajvee
• Jabeena Shaik

A high-throughput programmable fast Fourier transform (FFT) processor is designed supporting 16- to 4096-point FFTs and 12- to 2400-point discrete Fourier transforms (DFTs) for 4G, wireless local area network, and future 5G. A 16-path data parallel memory-based architecture is selected as a tradeoff between throughput and cost. To implement a hardware-efficient high-speed processor, several improvements are provided. To maximally reuse the hardware resource, a reconfigurable butterfly unit is proposed to support computing including eight radix-2 in parallel, four radix-3/4 in parallel, two radix-5/8 in parallel, and a radix-16 in one clock cycle. Twiddle factor multipliers using different schemes are optimized and compared, wherein modified coordinate rotation digital computer scheme is finally implemented to minimize the hardware cost while supporting both FFTs and DFTs.

IMPLEMENTATION OF DATA COMPRESSION SCHEMES USING FFT PROCESSORS FOR HIGH SPEED COMMUNICATION SYSTEMS

"IMPLEMENTATION OF DATA COMPRESSION SCHEMES USING FFT PROCESSORS FOR HIGH SPEED COMMUNICATION SYSTEMS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.8, Issue 8, page no.d390-d396, August-2021, Available :http://www.jetir.org/papers/JETIR2108420.pdf

"IMPLEMENTATION OF DATA COMPRESSION SCHEMES USING FFT PROCESSORS FOR HIGH SPEED COMMUNICATION SYSTEMS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.8, Issue 8, page no. ppd390-d396, August-2021, Available at : http://www.jetir.org/papers/JETIR2108420.pdf