UGC Approved Journal no 63975(19)

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Published in:

Volume 8 Issue 8
August-2021
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR2108619


Registration ID:
314593

Page Number

f142-f147

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Title

Implementation and Performance Improvement of 64 bit Posit Multiplier for High Speed VLSI-FPGA Processor

Abstract

A digital multiplier is an electronic circuit used in digital electronics, such as a computer, to multiply two binary numbers. A variety of computer arithmetic techniques can be used to implement a digital multiplier. This continuous improvement of the state of the art has been accompanied by an increase in computational complexity and an overhead in hardware resources. Posit number system has been used as an alternative to IEEE floating-point number system in many applications. The latency and speed is important parameter in digital multiplier. This paper proposed 64-bit posit multiplier for high speed VLSI-FPGA processor. Xilinx 14.7 is used to implementation with verilog programming language.

Key Words

Posit, Floating point, Xilinx 14.7, Multiplier, Verilog, Speed.

Cite This Article

"Implementation and Performance Improvement of 64 bit Posit Multiplier for High Speed VLSI-FPGA Processor", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.8, Issue 8, page no.f142-f147, August-2021, Available :http://www.jetir.org/papers/JETIR2108619.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"Implementation and Performance Improvement of 64 bit Posit Multiplier for High Speed VLSI-FPGA Processor", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.8, Issue 8, page no. ppf142-f147, August-2021, Available at : http://www.jetir.org/papers/JETIR2108619.pdf

Publication Details

Published Paper ID: JETIR2108619
Registration ID: 314593
Published In: Volume 8 | Issue 8 | Year August-2021
DOI (Digital Object Identifier):
Page No: f142-f147
Country: Patel Nagar, Madhya Pradesh, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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