• Juhi Bharti
• Dr. Bharti Gupta

The enhancement of the VLSI based circuit structure and parameter performance is going on to meet the requirement of the 5th generation FPGA internet of things applications. The security is major concern as developing the application under 5G-IOT. FPGA technology is upgrading to enhance the performance of latency and area. Many of the security algorithm is already developed but its less perform under advance FPGA-IOT constraints. The advance encryption standard is one of the best security algorithm and using in real time high secure application but its need to modify for FPGA-IOT applications. This paper proposes a high performance and area-efficient VLSI architecture of Modified S-Box with 256-bit Key. Modified-AES algorithm is a fast lightweight encryption algorithm for advance security with low latency. Simulation is performed using the Xilinx ISE 14.7 Software with verilog language. The simulation results are verified using Isim simulator in Xilinx test bench.

VLSI, FPGA, IOT, 5th G, Security, Cryptography, Encryption, Decryption, Xilinx ISE, Verilog

"VLSI Architecture of Modified S-Box with 256-bit Key for High Speed FPGA-IOT Applications ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.8, Issue 10, page no.c354-c358, October-2021, Available :http://www.jetir.org/papers/JETIR2110245.pdf

"VLSI Architecture of Modified S-Box with 256-bit Key for High Speed FPGA-IOT Applications ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.8, Issue 10, page no. ppc354-c358, October-2021, Available at : http://www.jetir.org/papers/JETIR2110245.pdf