UGC Approved Journal no 63975(19)

ISSN: 2349-5162 | ESTD Year : 2014
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Published in:

Volume 8 Issue 12
December-2021
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR2112158


Registration ID:
317784

Page Number

b488-b492

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Title

VLSI ARCHITECTURE OF MODIFIED S-BOX OF AES WITH 256-BIT KEY FOR HIGH SPEED FPGA-IOT APPLICATIONSVLSI ARCHITECTURE OF MODIFIED S-BOX OF AES WITH 256-BIT KEY FOR HIGH SPEED FPGA-IOT APPLICATIONS

Abstract

Security of multimedia data is an imperative issue because of fast evolution of digital data exchanges over unsecured network. Multimedia data security is achieved by methods of cryptography, which deals with encryption of data. Most of the application uses Advanced Encryption Standard (AES) and modify it, to reduce the calculation of algorithm and for improving the encryption performance. In modified AES algorithm used 1-Dimensionla S-box instead of 2-Dimensional S-box. This paper presents verilog Implementation of Modified Advanced Encryption Standard Algorithm using Xilinx Software. MAES is a lightweight version of AES which meets the demand. A new one-dimensional substitution Box (S-box) is proposed instead of conventional 2-D S-box and previous 1-D S-box.

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"VLSI ARCHITECTURE OF MODIFIED S-BOX OF AES WITH 256-BIT KEY FOR HIGH SPEED FPGA-IOT APPLICATIONSVLSI ARCHITECTURE OF MODIFIED S-BOX OF AES WITH 256-BIT KEY FOR HIGH SPEED FPGA-IOT APPLICATIONS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.8, Issue 12, page no.b488-b492, December-2021, Available :http://www.jetir.org/papers/JETIR2112158.pdf

ISSN


2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"VLSI ARCHITECTURE OF MODIFIED S-BOX OF AES WITH 256-BIT KEY FOR HIGH SPEED FPGA-IOT APPLICATIONSVLSI ARCHITECTURE OF MODIFIED S-BOX OF AES WITH 256-BIT KEY FOR HIGH SPEED FPGA-IOT APPLICATIONS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.8, Issue 12, page no. ppb488-b492, December-2021, Available at : http://www.jetir.org/papers/JETIR2112158.pdf

Publication Details

Published Paper ID: JETIR2112158
Registration ID: 317784
Published In: Volume 8 | Issue 12 | Year December-2021
DOI (Digital Object Identifier):
Page No: b488-b492
Country: Patel Nagar, Madhya Pradesh, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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