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Published in:

Volume 8 Issue 12
December-2021
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR2112323


Registration ID:
318097

Page Number

d183-d188

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Title

64-Bit Rounding Based Approximate Multiplier for High Speed Digital Signal Processing Applications

Abstract

A multiplier is an electronic circuit used in digital electronics, such as a computer, to multiply two binary numbers. It is built using binary adders. A variety of computer arithmetic techniques can be used to implement a digital multiplier. Multipliers play a key role in the present digital signal handling and different applications. With advances in innovation, numerous scientists have attempted and are endeavouring to structure multipliers which offer both of the following plan targets – high speed, low power utilization, consistency of design and henceforth less zone or even mix of them in one multiplier in this way making them appropriate for different high speed, low power and minimal VLSI usage. This paper proposed proposed 64 bit ROBA multiplier with improved performance then previous. Previous work, designed only 16 bit and 32 bit ROBA multiplier. Proposed 64-bit ROBA multiplier reduced 10% area than existing 32-bit multiplier, save 60% power. Proposed multiplier is giving 5% more accuracy than existing. Delay is significant constant so it can be say that it is improved than previous. The simulation is performed Xilinx 14.7 software.

Key Words

ROBA, VLSI, Multiplier, Speed, power, Xilinx

Cite This Article

"64-Bit Rounding Based Approximate Multiplier for High Speed Digital Signal Processing Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.8, Issue 12, page no.d183-d188, December-2021, Available :http://www.jetir.org/papers/JETIR2112323.pdf

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2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"64-Bit Rounding Based Approximate Multiplier for High Speed Digital Signal Processing Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.8, Issue 12, page no. ppd183-d188, December-2021, Available at : http://www.jetir.org/papers/JETIR2112323.pdf

Publication Details

Published Paper ID: JETIR2112323
Registration ID: 318097
Published In: Volume 8 | Issue 12 | Year December-2021
DOI (Digital Object Identifier):
Page No: d183-d188
Country: Patel Nagar, Madhya Pradesh, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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