• V. Srinivasa Rao
• K. Suresh Kumar

In this paper, as a preliminary methodology, the design of conventional Modified Booth multiplier and the design of Pre-Encoded NR4SD and NR8SD Multipliers have been discussed and then the architecture of High speed Non-Redundant radix-8 Signed-Digit (NR8SD) encoding method has proposed by using Han-Carlson adder, in which the digit values-3,-2,-1,0,+1,+2,+3,+4 or-4,-3,-2,-1,0,+1,+2,+3, are employed, resulting to a multiplier design with less difficult partial products implementation than NR4SD multiplier. The Modified Booth (MB) multiplier, which employs the digit values -2,-1, 0, +1 or-1,0,+1,+2, and where as the NR4SD multiplier saves space and allows for faster multiplication than the traditional Modified Booth Multiplier. These pre-encoded multipliers are based on off-line encoding, which allows DSP applications to generate fewer coefficients. Extensive experimental analysis verifies that the proposed pre-encoded NR8SD multipliers, including the coefficients memory, are more area and power-efficient than the conventional Modified Booth scheme. From the simulation results, it is revealed that the proposed NR8SD multiplier reduced area and delay compared to existing NR4SD and NR8SD multipliers.

NR4SD, NR8SD, DSP, Han-Carlson Adder

"DESIGN OF HIGH-SPEED MULTIPLIER BASED ON NON-REDUNDANT RADIX-8 ENCODING TECHNIQUE", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 5, page no.d323-d330, May-2022, Available :http://www.jetir.org/papers/JETIR2205459.pdf

"DESIGN OF HIGH-SPEED MULTIPLIER BASED ON NON-REDUNDANT RADIX-8 ENCODING TECHNIQUE", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 5, page no. ppd323-d330, May-2022, Available at : http://www.jetir.org/papers/JETIR2205459.pdf