• Ayushi Agrawal
• Dr. Prashant Chaturvedi

The demand for massive computation increases day by day. It leads to the requirement of high- speed adders for arithmetic operations. The high-speed adder consumes more area and power. The aim of this paper is to achieve low area of high speed adder without increasing the delay of the adder. The conventional BCD adder is very slow because of the huge carry chain delay. Therefore, a high-speed BCD adder with a KSA is proposed. In this design, a new detector circuit has been employed to generate the carry-out of each stage in two gate delays. This proposed BCD adder is faster than other existing BCD adders, but the area also rises. The binary to decimal converter was designed with new formulae so that it directly converts binary partial products to equivalent decimal number.

Kogge Stone Adder, Binary Coded Decimal (BCD), Delay

"Area Efficient High Speed BCD Adders using Modified Carry Select Adder", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 5, page no.g817-g821, May-2022, Available :http://www.jetir.org/papers/JETIR2205800.pdf

"Area Efficient High Speed BCD Adders using Modified Carry Select Adder", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 5, page no. ppg817-g821, May-2022, Available at : http://www.jetir.org/papers/JETIR2205800.pdf