• M. Harika Reddy
• S. Santhoshi Bhavani

The increasing complexity of the DSP systems demands higher computational performance in its architecture. But the traditional DSP arithmetic has limits in terms of speed of calculations. Moreover in some applications speed is more important than accuracy. In order to further enhance performance, approximate arithmetic circuits are designed with some loss of accuracy to reduce power consumption and increase speed. These approximate circuits have been considered for error-tolerant applications. In this paper, we propose a truncation and rounding-based approximate multiplier. In this multiplier, the operands are rounded to the nearest exponent of two and also used adder, and shifters at the final multiplication stage. This proposed multiplier will lead to simplification of multiplication operation thus reducing area, power and increasing speed. Simulation results reveal that the proposed approximate multiplier improves delay, area, and power consumption up to 9.3%, 37%, and 6.6%, respectively, compared to the ROBA multiplier. The proposed multiplier was synthesized and simulated using Xilinx Vivado 2016.4 environment.

Truncation, Rounding, Adders, Shifters, Approximate Computing, DSP.

"Efficient Design of Truncation and Rounding Based Approximate Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 6, page no.f198-f202, June-2022, Available :http://www.jetir.org/papers/JETIR2206526.pdf

"Efficient Design of Truncation and Rounding Based Approximate Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 6, page no. ppf198-f202, June-2022, Available at : http://www.jetir.org/papers/JETIR2206526.pdf