UGC Approved Journal no 63975(19)

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Published in:

Volume 9 Issue 6
July-2022
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR2206A18


Registration ID:
405275

Page Number

k157-k163

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Title

A HIGH PERFORMANCE GATE DIFFUSION INPUT TECHNIQUE BASED FULL SWING AND SCALABLE 1-BIT HYBRID FULL ADDER

Abstract

A compact fluid cell is based on Gate Diffusion Input (GDI) and Conventional Complementary Metal-Oxide Semiconductor (CCMOS) then it is known as the Full Adder (FA) and these concepts were proposed for the task. Computer Aided Design (CAD) tool in a 45 nm CMOS process has been used for the simulation. Exceptional performance improvements were observed in the proposed design in terms of Product Delay (PDP) and speed. In order to test performance criterions on larger portions, the FAs were reduced and expanded to 32 bits. The five of the ten existing projects worked impeccably when they were expanded to 32 bits as well as the proposed design. Furthermore, the best performance criterion was achieved in large cascade circuits by the main proposed design. A FA is a complementary logic circuit that adds two input electrons into a sum of one's. The circuit consists of 3 1-input binary adding units, which are called "flippers". Each 1-input binary adding unit consists of first and second inverters having zero input bias voltage and one output with an intermediate state. When both of the two input electrons are "0", the first and second inverters will be off i.e., all their output voltages are zero. But when an input electron is a "1", its corresponding first and second inverters will turn on, providing an intermediate output voltage (V) for its summing up with second inverter. With this intermediate output voltage, the third inverter can cross add the binary numbers of these 1-input adding units to get their final binary sum which is called FA's sum.

Key Words

GDI, CCMOS, PDP

Cite This Article

"A HIGH PERFORMANCE GATE DIFFUSION INPUT TECHNIQUE BASED FULL SWING AND SCALABLE 1-BIT HYBRID FULL ADDER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 6, page no.k157-k163, June-2022, Available :http://www.jetir.org/papers/JETIR2206A18.pdf

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2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"A HIGH PERFORMANCE GATE DIFFUSION INPUT TECHNIQUE BASED FULL SWING AND SCALABLE 1-BIT HYBRID FULL ADDER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 6, page no. ppk157-k163, June-2022, Available at : http://www.jetir.org/papers/JETIR2206A18.pdf

Publication Details

Published Paper ID: JETIR2206A18
Registration ID: 405275
Published In: Volume 9 | Issue 6 | Year July-2022
DOI (Digital Object Identifier):
Page No: k157-k163
Country: Hyderabad, Telangana, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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