• Harshwardhan Singh
• Prof. Suresh S. Gawande

In this work, single bit modulator and decimator filter for audio codec applications is described as a MATLAB® SIMULINK® model. Together with the different non-idealities and noise models related to the modulator, the delta-sigma ADC is constructed. For Audio Codec applications that demand great precision at the required input frequency, this kind of modulator is created. At an output data rate of 48 KS/s, the targeted SNR in this case is a minimum of 100 dB. A 4th order 1-bit CIFF Modulator structure is the Simulink® model that is being presented. The performance of ideal modulators can be impacted by a variety of non-idealities, such as practical GBW, switch noise, clock jitter, and finite DC gain; hence in this work, the non-idealities have been added for all stages and optimized them for achieving the 10dB Dynamic Range with practical conditions. In order to achieve the 10dB Dynamic Range under realistic circumstances, non-idealities have been included for all stages and optimized.

Sigma-Delta Modulator (Z∆ Modulator), GBW (Gain Bandwidth product), TF (Transfer Function), BW (Bandwidth), SR (Slew rate), SNR (Signal to Noise Ratio).

"Modelling, Characterization and Optimization of a Delta-Sigma ADC for Audio Codec Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 7, page no.d464-d468, July-2022, Available :http://www.jetir.org/papers/JETIR2207360.pdf

"Modelling, Characterization and Optimization of a Delta-Sigma ADC for Audio Codec Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 7, page no. ppd464-d468, July-2022, Available at : http://www.jetir.org/papers/JETIR2207360.pdf