• Deepak Kumar Tiwari
• Abhishek Shrivastava

Static Random-Access Memory (SRAM) with ultra-low power consumption is required in Internet of Things (IoT) devices to ensure long battery life. The current work employs the Cadence Virtuoso tool for the execution of 7T SRAM cell methods, & all considered methodologies' read & write operations have been carefully monitored. The goal of this work is to decrease 7T SRAM cell power while maintaining industry-leading performance. Microprocessors, Cache memories, & portable devices are just a few examples of the many applications where SRAM is crucial. Leakage power is the main issue with SRAM cells when it comes to low-power applications as the node of the technology is scaling down. Consequently, low power appropriate memory design is required. The key to using the anti-body bias approach to a 7T SRAM cell is to lower the bulk voltage, low power, & leakage current. This reduces process variation. We look into anti-body biassing as a means of controlling the bulk voltages of transistors, and we demonstrate that it works especially well in sub-threshold circuits and can completely remove performance differences and weak power.

SRAM, CMOS, Cadence, 7T SRAM Cell, Leakage Power.

"Performance Analysis of 7T SRAM Cell IOT-based devices using Anti Body Bias Technique ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 7, page no.h51-h54, July-2022, Available :http://www.jetir.org/papers/JETIR2207709.pdf

"Performance Analysis of 7T SRAM Cell IOT-based devices using Anti Body Bias Technique ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 7, page no. pph51-h54, July-2022, Available at : http://www.jetir.org/papers/JETIR2207709.pdf