• V.SATHISH
• Dr.B.NAGESHWARRAO
• Dr.T.Vamsi

It is clear that deep learning, as a new branch of machine learning, is capable of addressing complex learning issues with ease. However, due to the needs of real applications, the complexity of the networks grows significantly, making it difficult to implement high-performance deep convolution neural network neural networks. DLAU is a hardware prototype for a scalable acceleration design for large-scale deep learning networks that uses a field-programmable gate array (FPGA) as a hardware prototype to boost performance and preserve low power consumption. Deep learning applications benefit from the DLAU accelerator's exploration of locality using tile techniques and three pipelined processing units. The latest Xilinx FPGA board shows that the DLAU accelerators can outperform Intel Core2 processors in terms of speed.

Deep learning, field-programmable gate array (FPGA), hardware accelerator, neural network.

"An Effective Optimization of FPGA Based Scalable Deep Learning Accelerator Unit (DLAU) for Deep Convolution Neural Networks.", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 8, page no.e640-e647, August-2022, Available :http://www.jetir.org/papers/JETIR2208476.pdf

"An Effective Optimization of FPGA Based Scalable Deep Learning Accelerator Unit (DLAU) for Deep Convolution Neural Networks.", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 8, page no. ppe640-e647, August-2022, Available at : http://www.jetir.org/papers/JETIR2208476.pdf