• G.SRAVANI
• Dr.B.Nageshwar Rao
• Dr.T.Vamsi

These two small design approaches, data-driven clocking and multi-bit flip-flops, use a common clock controller to drive several FFs at the same time. Separately, these are usually applied by VLSI designers. MBFF utilization in RTL, gate-level, and their arrangement have been the focus of previous studies. There were tensions and contradictions between different aspects of a project that were all studied together as a whole. Internal circuit diagram, its multiplicity and synergy with FF data flashing chances have not been examined thus far. This paper proposes a DDCG and MBFF combination algorithm based on the data-to-clock toggling ratio of Flip-Flops (FFs) in order to maximize energy savings. According to the results, the MBFFs should be arranged in order of increasing of activity to save the most electricity possible. It is possible to reduce the amount of power consumed by a device by employing a power-saving model that makes use of MBFF algebraic expressions and FF toggling probabilities. By using the Xilinx ISE tool, we were able to save between 17% and 23% of power in comparison to design with conventional Flip-Flops, which was around 39%.

-Flops, MBFF,2-bit MBFF, k –MBFF, pCQ t.

"DESIGN AND OPTIMIZATION PROBABILITY-DRIVEN MULTI BIT FLIP-FLOP WITH CLOCK GATING TECHNIQUES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 8, page no.f31-f38, August-2022, Available :http://www.jetir.org/papers/JETIR2208505.pdf

"DESIGN AND OPTIMIZATION PROBABILITY-DRIVEN MULTI BIT FLIP-FLOP WITH CLOCK GATING TECHNIQUES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 8, page no. ppf31-f38, August-2022, Available at : http://www.jetir.org/papers/JETIR2208505.pdf