• Mohammedsharukhpasha
• Dr.B.Nageshwar Rao
• Dr.T.Vamsi

Applications that make use of machine learning (ML) frequently make use of decision trees (DTs) because of the ease with which they can be interpreted and the speed with which they can be executed. Because DT training takes a significant amount of time, in this condensed version, we presented a hardware training accelerators as a means of accelerating the learning process. This field-programmable- gate -array (FPGA) with a maximum allowable frequency of 62 MHz is used to create the suggested training accelerator. The suggested architecture makes use of a combination of pipelined execution and parallel execution in order to reduce the amount of time needed for training and to use as little resources as possible. It has been determined that the C-based application software is at least 14 times slower than the proposed hardware design when it comes to a certain design. In addition, the suggested architecture merely requires a specific RESET signal in order to be readily retrained in order to process that this next set of data. Because of this form of training, the hardware can be used for a wide variety of different applications.

Decision tree (DT), field-programmable gate array (FPGA), machine learning (ML), training accelerator, two means DT (TMDT).

"HIGH PERFORMANCE FPGA BASED TRAINING ACCELERATOR FOR TWO MEANS DECISION TREE", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 8, page no.f604-f614, August-2022, Available :http://www.jetir.org/papers/JETIR2208564.pdf

"HIGH PERFORMANCE FPGA BASED TRAINING ACCELERATOR FOR TWO MEANS DECISION TREE", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 8, page no. ppf604-f614, August-2022, Available at : http://www.jetir.org/papers/JETIR2208564.pdf