• Jyoti Soni
• Dr. M Zahid Alam

Cryptography plays an important role in the security of data transmission. The security is major concern as developing the application under 5G-IOT. FPGA technology is upgrading to enhance the performance of latency and area. Many of the security algorithm is already developed but its less perform under advance FPGA-IOT constraints. The advance encryption standard is one of the best security algorithm and using in real time high secure application but its need to modify for FPGA-IOT applications. This paper proposes FPGA implementation of modified cryptography for VLSI security Applications. Modified-AES algorithm is a fast lightweight encryption algorithm for advance security with low latency. Simulation is performed using the Xilinx ISE 14.7 Software with verilog language. The simulation results are verified using Isim simulator in Xilinx test bench.

"FPGA Implementation of Modified Cryptography for VLSI Security Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 9, page no.a580-a585, September-2022, Available :http://www.jetir.org/papers/JETIR2209060.pdf

"FPGA Implementation of Modified Cryptography for VLSI Security Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 9, page no. ppa580-a585, September-2022, Available at : http://www.jetir.org/papers/JETIR2209060.pdf