• MUMMAREDDY.RAMYA KRISHNA

Arithmetic operations play a crucial role in signal processing applications, micro processors, and micro controllers. Multiplication operation is widely used in Digital Signal Processing (DSP) modules like Infinite Impulse Response (IIR) filters, Finite Impulse Response (FIR) filters, Discrete Fourier Transform (DFT),Fast Fourier Transform (FFT), Discrete Cosine Transform (DCT) and etc. Reducing the power dissipation and increasing the performance is the most important challenge for multiplier design. Power reduction techniques such as Recoding (RADIX- 8 Modified Booth Encoding (MBE)) structure has different logic combinations to generating Partial Product Rows (PPRs) which is used in modified pipelined multiplier. Two additionapproaches like tree based Carry Look-a-head Adder (CLA) and sequential based CLA are used for addition between generated PPRs. Performance comparison between existed RADIX-4 pipelined multiplier and RADIX-8 pipelined multiplier with aboveaddition approaches, the modified method yieldsconsiderablemoderatecritical path delay, area and reduced the power consumption. Modified design is implemented in XILINX 14.7withFPGAtechnologyXC3S500E-FG320-5.

PPR, Modified booth Encoding, CLA, Pipelined Multiplier

"Design and Analysis of Radix-8 Structure based 32-bit Pipelined Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 9, page no.e142-e148, September-2022, Available :http://www.jetir.org/papers/JETIR2209418.pdf

"Design and Analysis of Radix-8 Structure based 32-bit Pipelined Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 9, page no. ppe142-e148, September-2022, Available at : http://www.jetir.org/papers/JETIR2209418.pdf