• Vaka.Venkata Ramanamma

In microprocessors, DSPs, different kinds of arithmetic building blocks such as adder, subtractor, multiplier and divider are required to compute binary data. The priority of data path can be operation speed, low power consumption, area or design time. The most important design goals in many cases are area and low power consumption. The basic structure in any arithmetic block is an adder circuit. Hence, by optimizing the adder circuit, area and low power consumption can be achieved. Several kinds of adders have been proposed to reduce the worst-case propagation delay from Least significant bit(LSB) to Most significant bit(MSB). The Carry select adder is one of the adder architectures that reduces the carry propagation delay by grouping sub-block of adders. Many techniques can be used to improve the CSA performance as proposed by researchers in previous work that is, by using BEC-1(Binary to eccess-1 converter), using D-Latch etc. In this work, the CSA is designed using GDI(Gate diffusion input) technique and using both GDI and MTCMOS D-Latch to achieve better performance as compared to previous work. Tanner and Mentor Graphics 250nm CMOS Technology is used for simulation. The design of CSA using GDI logic achieved a tremendous improvement in power consumption and Transistor count of 99.45% and 58.85% respectively as compared to the conventional CSA.

CSA, MTCMOS D-Latch, GDI, Low Power, High Speed

"Performance Analysis of a Low Power and Area 8-Bit Carry Select Adder", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 9, page no.e174-e178, September-2022, Available :http://www.jetir.org/papers/JETIR2209422.pdf

"Performance Analysis of a Low Power and Area 8-Bit Carry Select Adder", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 9, page no. ppe174-e178, September-2022, Available at : http://www.jetir.org/papers/JETIR2209422.pdf