• Lakshmi Durga Nujiveeti
• R Vinay Kumar

Static Random Access memory (SRAM) is a memory component. Due to its unique capability to retain data, there is a large demand for SRAM in SOC with large usage. This memory component became a research subject to meet future demands With increase in SRAM density, significance of the power leakage has increased in chip design. In recent years, power reduction in SRAM is undergoing tremendous advancement Mary techniques have been devised to achieve active and standby reduction in both dynamic and static power. Performance in terms of speed and power dissipation is the major concern in today's memory technology. Keeping this in view, this paper emphasizes a low power SRAM using hybrid sleep transistor technique which is compared in terms of delay: power dissipation and power delay product(PDP) to that of conventional SRAM. This technique reduces both delay and power consumption of SRAM. Whole work is done on the TANNER MENTORGRAPHICS 250nm technology parameter & stimulated are IV supply voltage.

NMOS,PMOS,CMOS, SRAM,SRAM, System on chip(Soc), MTCMOS, Scaling

"A Low Power 6T SRAM using Sleep Power Reduction Technique", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 9, page no.e346-e349, September-2022, Available :http://www.jetir.org/papers/JETIR2209439.pdf

"A Low Power 6T SRAM using Sleep Power Reduction Technique", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 9, page no. ppe346-e349, September-2022, Available at : http://www.jetir.org/papers/JETIR2209439.pdf