• Dudala V. N. V. Pavan Raj Kumar
• Y. Syamala

In many applications, the floating numbers are generally represented with the use of IEEE floating point number system. With the advancement of the technology the IEEE floating numbers are replaced by posit number system. In general multipliers consume high power and delay in arithmetic operations. The posit number system reduces these parameters with the maximum bit width of the mantissa. These multipliers are usually used in MAC units, in DSP processors, signal processing, graphics and scientific computations. The posit number systems are designed for the reduction of the propagation time and reducing the complexity of the floating point multiplications. The posit encoder and decoder are designed in the processor registers to further reduction of the area overhead. In this paper implementing of Posit Multiplier using Virtex 7 FPGA family.

Floating point, Posit number system, Multiplier

"Design And Implementation Of Posit Multiplier ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 10, page no.b583-b587, October-2022, Available :http://www.jetir.org/papers/JETIR2210183.pdf

"Design And Implementation Of Posit Multiplier ", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 10, page no. ppb583-b587, October-2022, Available at : http://www.jetir.org/papers/JETIR2210183.pdf