• Pinniboyina Anand Venkat Seshu Babu
• K. Rajasekhar

The paper presents a new approach to rapid counters, including binary counters, approximation (4:2) compressors, and so on, all based on a sorting network. In order to speed things up, a high compressor counter is required. After the counter inputs are asymmetrically divided in half, they are used as inputs to arranging organizations to produce arrangements that can be addressed by basic one-hot code groupings. The (7:3) counter, which can be built and developed using this way, outperforms other designs in terms of latency, overall size, and power consumption in most situations. The result is a counter with a factor of 15, which has the advantages of lower power consumption and smaller footprint, but at the expense of increased latency. As an extra, we use approximation compressors that employ a sorting network (4:2). They made a 8 x 8, 16 x 16 digit multiplier to test the viability of their circuits. Viability of a 24Bit multiplier configuration is delivered and reproduced in Xilinx Vivado.

"A LINEAR 24 BIT MULTIPLIER WITH VLSI APPLICATIONS USING SORTING BASED BINARY COUNTERS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 10, page no.d148-d154, October-2022, Available :http://www.jetir.org/papers/JETIR2210332.pdf

"A LINEAR 24 BIT MULTIPLIER WITH VLSI APPLICATIONS USING SORTING BASED BINARY COUNTERS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 10, page no. ppd148-d154, October-2022, Available at : http://www.jetir.org/papers/JETIR2210332.pdf