• URLA HEMANTH
• Dr U.V.Ratna Kumari

The research into finite field multiplication has gained a significant amount of interest due to its prominent applications in cryptography and error detection codes. This cryptographic arithmetic technique is a laborious task that is not only costly but also takes a significant amount of time. It requires millions of gates. The research conducted for this particular investigation of a cryptographic algorithm suggests an effective hardware architecture for all cryptographic applications that is based on cyclic redundancy check (CRC) as an error detection method. This work introduces an architecture for digit serial multiplication in finite fields GF, with applications to cryptography. GF stands for Galios finite fields (2m). The steps of multiplication and degree reduction are alternated within the framework of the suggested system, which is based on the representation of polynomial bases. A multiplier with M bits may be used for calculations in any binary field of order, and it is compatible with any irreducible polynomial. Therefore, the Versatile and Scalable Digit Serial/Parallel Multiplier Architecture for Finite Field will be merged with the Reliable CRC implementation and design of GF(23) = 8-Bit, GF(24) = 16-Bit, and GF(25) = 32-Bit based CRC Error detection. This work was created using Verilog HDL, and it was then synthesized using Vertex-5 FPGA. After that, all of the parameters like area, delay, and power are obtained.

Galios Finite Field(GF) ,Finite Field Multiplier,Cyclic Redundancy Check(CRC),Cryptography,Error Detection.

"Implementation of Reliable CRC Error Detection For Highly Flexible and Scalable Digit Serial / Parallel Finite Field Multiplier on FPGA for Cryptography Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 10, page no.d286-d292, October-2022, Available :http://www.jetir.org/papers/JETIR2210349.pdf

"Implementation of Reliable CRC Error Detection For Highly Flexible and Scalable Digit Serial / Parallel Finite Field Multiplier on FPGA for Cryptography Applications", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 10, page no. ppd286-d292, October-2022, Available at : http://www.jetir.org/papers/JETIR2210349.pdf