• Mr. KAMARATHI NAVEENKUMAR
• Mrs.B.KEERTHI
• Mr.N.NAGENDRA

Dynamic power, which includes switching power and internal power, is the primary contributor to overall power consumption in CMOS-based ASIC designs. We investigate the concept of a low-power, precision-tunable multiplier. Numerous error-tolerant programmes utilize multiplication as a core operation. Multiplication by approximation is an effective and accurate method for balancing energy use. This article offers a carry-masking adder with a precision- controllable multiplier output. The suggested method may meet the accuracy requirements by dynamically modifying the carry propagation period. The proposed tree compressor is a close approximation of the multiplier's partial product tree. A multiplier is built using the carry mask able adder and the compressor. The multiplier presented utilized less energy than a conventional multiplier. The Xilinx-ise verilog HDL programming language is utilized to perform and record implementation, synthesis, and simulation.

ICAC, ATC, Carry mask able adder and controllable approximation method.

"DESIGN OF AREA EFFICIENT VLSI ARCHITECTURE OF APPROXIMATE MULTIPLIER USING CARRY MASKABLE ADDER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 11, page no.a254-a260, November-2022, Available :http://www.jetir.org/papers/JETIR2211032.pdf

"DESIGN OF AREA EFFICIENT VLSI ARCHITECTURE OF APPROXIMATE MULTIPLIER USING CARRY MASKABLE ADDER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 11, page no. ppa254-a260, November-2022, Available at : http://www.jetir.org/papers/JETIR2211032.pdf