• Mr. Bukkasam MadhuSudhan
• Mr. B.C.Vengamuni
• Dr .Gannera Mamatha

The Serial-Peripheral Interface (SPI) protocol is one of the most widely used bus protocols for connecting processors to peripheral devices with low/medium data transmission speeds. SPI architecture is used to communicate between multiple peripherals and the processor in a SoC application. The slave is subject to the master's power. The slave is represented by a sensor, monitor, or memory chip. A reusable logic or functionality unit, cell, or layout design that can be used in numerous chip designs is referred to as an intellectual property (IP) in the context of VLSI. These IPs are typically created with the intention of licensing them to other vendors. This IP verification of the SPI controller is done by writing test benches in System Verilog and UVM. This paper’s aim is to verify Intellectual Property (IP) blocks and driver development of SPI controller for Open-Power processor A2O core-based fabless SoC connected through AXI4 interface. The methodology used for verifying is to develop Test benches in System Verilog and use them for Verification by using software like ModelSim Questa® and Vivado design suite-Xilinx®.

System Verilog, UVM, Testbench, SoC, SPI, AXI4

"IP VERIFICATION OF SPI CONTROLLER FOR OPEN POWER PROCESSOR CORE BASED FABLESS SYSTEM ON CHIP (SoC)", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 11, page no.e215-e221, November-2022, Available :http://www.jetir.org/papers/JETIR2211439.pdf

"IP VERIFICATION OF SPI CONTROLLER FOR OPEN POWER PROCESSOR CORE BASED FABLESS SYSTEM ON CHIP (SoC)", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 11, page no. ppe215-e221, November-2022, Available at : http://www.jetir.org/papers/JETIR2211439.pdf