• Chamarthi Tejaswini
• K.Babitha

In this paper the aim is to perform high speed three operand addition. Three operand binary adders are the basic functional unit to perform modular arithmetic in various cryptography and pseudorandom bit generator(PRBG) algorithms.Binary adders are known as important elements in the circuit designs. Many fastest adders have been created and developed. Parallel Prefix Adders (PPA) are one among them. We use adders frequently in digital design and VLSI designs, in digital design we use adders such as half adder, full adder which are serial type. By using both adders we can perform addition for any number of bits. But it has a huge delay problem. To overcome this, Parallel Prefix Adders are preferred. In VLSI implementation parallel prefix adders are known to have the best performance. This paper presents an implementation of various types of carry tree adders like the Kogge- Stone, Brent Kung, Han Carlson, and Ladner Fischer and compares them with serial adders. Hence, a new high speed adder architecture is proposed.

"DESIGN OF HIGH SPEED THREE OPERAND ADDER USING PARALLEL PREFIX ADDERS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 12, page no.b313-b321, December-2022, Available :http://www.jetir.org/papers/JETIR2212135.pdf

"DESIGN OF HIGH SPEED THREE OPERAND ADDER USING PARALLEL PREFIX ADDERS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 12, page no. ppb313-b321, December-2022, Available at : http://www.jetir.org/papers/JETIR2212135.pdf