• Parvathala Sreenivasulu
• M.Aarif Ahmed

Approximate computing device in a digital system reduces the design complexity and provide the high efficient solutions in order to increases its performance. The exact computing device is not always necessary for multimedia signal processing and data mining, which are capable of tolerate error. The proposed design of the approximate multiplier can able to reduce the design complexity and reduces its area in order to increases its performance. In this paper approximate multiplier, Truncation concept is used in order to reduces its area as well as power consumption when compared to normal approximate multiplier which is used in the existing system. This multiplier technique is fully focused on partial products accumulation which is very important in terms of power consumption. Therefore, the proposed truncation multiplier saves few adders in partial products, and evaluated with a image processing application. The existing system focused only on luminance based application, but the proposed work focused on both luminance and chrominance based application. Finally implement this proposed work in VHDL and synthesized in the XILINX-S6LX9 FPGA and compared in terms of area, power and delay reports.

"DESIGN OF POWER AND AREA EFFICIENT HSCG-SCG BASED MULTIPLIER FOR GAUSSIAN FILTER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 12, page no.b334-b349, December-2022, Available :http://www.jetir.org/papers/JETIR2212137.pdf

"DESIGN OF POWER AND AREA EFFICIENT HSCG-SCG BASED MULTIPLIER FOR GAUSSIAN FILTER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 12, page no. ppb334-b349, December-2022, Available at : http://www.jetir.org/papers/JETIR2212137.pdf