• T Poojitha
• K.Mamatha, M.Tech.,(Ph.D),
• Dr.Gannera Mamatha M.Tech., Ph.D

The modern mainstream of IC innovation is SoC (System-on-a-Chip), which is the modern international VLSI latest generation. According to Moore's Law, as transistor dimensions get smaller, IC complexity on a chip has been growing rapidly. The primary problem in SoC design is to effectively integrate various IP cores and keeping their capacity to carry out specified tasks and interact with one another; thus, it is necessary to confirming the quality of integration at the SoC level. Ethernet is a bi –directional networking protocol which governs and specifies way data interacts through a data transmission in both directions. The hardware enables 10/100/1000Mbps using its Ethernet MAC module. Incorporating Media Independent Interface (MII) enables time-sensitive applications over bridged Local area network (LAN) also with AXI4 Master interface and AXI4 Slave interface, Ethernet MAC is compliant with IEEE 802.3 standard. It supports CSMA/CD Protocol. In this paper, the design and validation of an AXI bus-based MAC controller are discussed

Keywords- AXI bus; Media Access Control; Verification Methodology Manual; System Verilog; Verilog

"IP Level Verification of Ethernet Protocol for OpenPOWER Processor Core based Fabless System on Chip (SoC)", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.9, Issue 12, page no.c130-c135, December-2022, Available :http://www.jetir.org/papers/JETIR2212220.pdf

"IP Level Verification of Ethernet Protocol for OpenPOWER Processor Core based Fabless System on Chip (SoC)", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.9, Issue 12, page no. ppc130-c135, December-2022, Available at : http://www.jetir.org/papers/JETIR2212220.pdf