• Rajanikant
• Dr Ravi Shankar Mishra

Reversible logic computation is one of the most essential promising technologies in designing low-power digital circuits, optical information processing, quantum dot cellular automata, fault tolerant system and nanotechnology. In fact, the conventional digital circuits dissipate a significant amount of energy because several bits of information are deleted during the treatments. In reversible computation, the information bits are not lost. This paper presents the study of reversible realization of adder-subtractor circuit.

Digital, Reversible, Realization, Adder, Subtractor.

"Review of CMOS Reversible Gates Logic for Low Power and Delay FPGA Application", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 1, page no.e757-e760, January-2023, Available :http://www.jetir.org/papers/JETIR2301499.pdf

"Review of CMOS Reversible Gates Logic for Low Power and Delay FPGA Application", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 1, page no. ppe757-e760, January-2023, Available at : http://www.jetir.org/papers/JETIR2301499.pdf