• Pankaj Kumar
• Santosh Onker

In the modern era of Advance science and technology today the performance of the memory is the main part of the computer system that needs to be improved. In computer applications including laptops, networking and DSP processing systems DDR SDRAM is frequently used. Memory controllers enable efficient data control between the processor and memory. Any design flow must include verification because it is finished before silicon development. It is carried out during the product development process to verify for quality and fix design bugs. A memory controller for Double Data rate synchronized dynamic random-access memory (DDR SDRAM) is designed in this work, and a coverage-driven constraint random verification environment is built for the designed memory controller. The DDR SDRAM controller do many tasks like refresh, initialization and timings that is unaware to the user. The use of appropriate commands, such as Read and Write accesses, appropriate active and pre-charge commands, etc is another goal in the design of DDR SDRAM controller. System Verilog is used for the verification while the code is written in Verilog HDL. Although the DDR SDRAM controller's core functions are the same as those of SDR (Single Data Rate) SDRAM, but the circuit design is different. DDR merely uses complex circuit techniques to achieve high speed. DDR SDRAM employs a double data rate design to increase the number of operations per clock cycle. Data is sent on both the rising and falling edges of the clock in DDR SDRAM, also referred to as DDR (Double Data Rate). The DDR controller is made with the intention of providing the correct commands for SDRAM start, read/write operations, routine refresh operations, appropriate active and pre-charge commands, etc. Verilog HDL is used to implement the DDR SDRAM controller, and ISim and Xilinx ISE Design suite 14.7 are used for simulation and synthesis, respectively.

DDR , SDRAM, Verilog, Memory Controller

"A Comprehensive Study Of Design And Verification Of DDR SDRAM Controller Using Verilog", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 1, page no.f448-f453, January-2023, Available :http://www.jetir.org/papers/JETIR2301560.pdf

"A Comprehensive Study Of Design And Verification Of DDR SDRAM Controller Using Verilog", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 1, page no. ppf448-f453, January-2023, Available at : http://www.jetir.org/papers/JETIR2301560.pdf