• Chandana C D
• Dr. Meera. A

Each technology node brings a new set of challenges and complex changes to the designs. Increase in the memory blocks requires large amount of area in the chip with the increased test time and faults are observed at each cell. As the memories are designed very dense, results in the escaping of many faults during the testing. Built in self-test (BIST) is the one of the optimistic methodology to test the memories. This work presents the Ratio test method to detect the escaping faults which intern helps to reduce the production test cost with specific set of BIST algorithms. In order to remove the test time problems, we proposed the test time reduction techniques which defines the time to market goals. Ratio test method shows the early detection of design issue bugs and test time is reduced upto 70%.

Built in self-test (BIST), Ratio test method, Test time Reduction techniques, Memory block.

"ATE Characterization and Test Time Reduction Techniques in validation environment", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 2, page no.c661-c665, February-2023, Available :http://www.jetir.org/papers/JETIR2302286.pdf

"ATE Characterization and Test Time Reduction Techniques in validation environment", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 2, page no. ppc661-c665, February-2023, Available at : http://www.jetir.org/papers/JETIR2302286.pdf