• Nagamalli. Arasavalli
• Balaji Abburi
• Manideep P
• Teja T
• Nasiha Farheen SK,Kavya S

In the era of Big data, Internet of Things (IoT), Industry 4.0 and 5G communication based applications where high speed computations with minimal or reduced faults and errors are intended. Digital signal processing (DSP) multiplier and accumulator (MAC) structures are the core building blocks in which integer or float point multiplications from low to high complexity computations at higher speeds are expected in this Digital era. Systolic Array Matrix Multiplier (SAMM) is implemented in which Fault Tolerance can be expected such that it can detect logic level faults and timing errors due to intermittent clocks at transistor level. The SAMM process element (PE) architectures using Verilog HDL in Xilinx Vivado are implemented results with reduced error less MAC units at higher complex operations with reduced voltages, detecting errors on-the-fly to avoid energy demanding round-trips over the complex computations are achieved.

fault detection, systolic array, matrix multiplication, hardware and Network architectures.

"IMPLEMENTATION OF FAULT TOLERANT SYSTOLIC ARRAY MATRIX MULTIPLIER AS PROCESS ELEMENT BLOCKs FOR HIGHSPEED COMPUTATIONS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 3, page no.f400-f403, March-2023, Available :http://www.jetir.org/papers/JETIR2303549.pdf

"IMPLEMENTATION OF FAULT TOLERANT SYSTOLIC ARRAY MATRIX MULTIPLIER AS PROCESS ELEMENT BLOCKs FOR HIGHSPEED COMPUTATIONS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 3, page no. ppf400-f403, March-2023, Available at : http://www.jetir.org/papers/JETIR2303549.pdf