• B.Sumaja
• CH.Mounika
• K.Pravallika
• J.Reshma
• CH.Vishnupriya

This paper mainly concentrated on to lessen the power consumption of the ADC by optimizing encoder circuitry. With the purpose of reducing power consumption , Encoder is implemented using 2:1 mux based on CMOS logic. Performance parameters of Flash ADC such as delay as well as average power are calculated and compared. In this paper, Flash Analog to digital convertor is implemented whose resolution is 3-bits.The designed Flash ADC consists of a resistive ladder network, comparators, the thermometer to a binary encoder and the entire design is carried out using Tanner Tools employing 180nm technology. The reference voltage applied to the resistive ladder network is 1.8V. A two-stage operational amplifier is used as a comparator in the flash ADC. Binary code is obtained from the thermometer code by utilizing a encoder.

Two-Stage Operational Amplifier, Flash ADC and Encoder using MUX

"DESIGN AND IMPLEMENTATION OF HIGH PERFORMANCE OF 3-BIT FLASH ADC", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 4, page no.g311-g318, April-2023, Available :http://www.jetir.org/papers/JETIR2304845.pdf

"DESIGN AND IMPLEMENTATION OF HIGH PERFORMANCE OF 3-BIT FLASH ADC", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 4, page no. ppg311-g318, April-2023, Available at : http://www.jetir.org/papers/JETIR2304845.pdf