• Kasturi Akash
• Chintam Shravan
• A Nagajyothi

Embedded memories are critical components in modern microprocessors and other VLSI systems-on-chip (SoCs). Such memories consume an ever-growing share of the total silicon area and significantly contribute to the leakage power of the system. This paper presents a novel 5T memory cell model that builds upon the 4T Gain-Cell with internal-feedback technology proposed in referred paper. The new design incorporates an additional transistor to further improve data retention time and reduce power consumption. The proposed bit cell and operation mechanisms of this technology are described, and simulation results are presented to demonstrate its effectiveness. Compared to traditional SRAM and existing 4T Gain Cell embedded Dynamic Random Access Memory (GCeDRAM), the 5T model achieves higher density, lower leakage, and lower power consumption.

GC-eDRAM, Storage Node, gain cell, Monte Carlo Simulations, DRT, Leakage Power.

"Storage node and Power analysis of 5-Transistor GC-eDRAM for longer Retention time", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.10, Issue 5, page no.e369-e378, May-2023, Available :http://www.jetir.org/papers/JETIR2305455.pdf

"Storage node and Power analysis of 5-Transistor GC-eDRAM for longer Retention time", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.10, Issue 5, page no. ppe369-e378, May-2023, Available at : http://www.jetir.org/papers/JETIR2305455.pdf