UGC Approved Journal no 63975(19)
New UGC Peer-Reviewed Rules

ISSN: 2349-5162 | ESTD Year : 2014
Volume 12 | Issue 12 | December 2025

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Published in:

Volume 11 Issue 1
January-2024
eISSN: 2349-5162

UGC and ISSN approved 7.95 impact factor UGC Approved Journal no 63975

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Published Paper ID:
JETIR2401160


Registration ID:
531142

Page Number

b523-b533

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Title

DESIGN AND IMPLEMENTATION OF HALF ADDER AND FULL ADDER USING REVERSIBLE LOGIC GATES

Abstract

In the realm of digital electronics, efficient and versatile circuit design is paramount. This paper presents a novel approach to designing a Full Adder circuit using unconventional gates, namely the Peres gate, Fredkin gate, NOT gate, and Feynman gate. These gates have distinct characteristics that make them suitable for complex circuitry, offering potential advantages in terms of speed, power efficiency, and scalability. The Peres gate, a three-input quantum gate, allows for reversible computation and is employed to enable arithmetic operations in our Full Adder circuit. The Fredkin gate, known for its ability to perform reversible data swapping, plays a pivotal role in managing carry operations within the circuit. The NOT gate is a fundamental element for inverting binary inputs, while the Feynman gate serves as a versatile unit capable of performing multiple logical operations. This project aims to demonstrate the feasibility of constructing a Full Adder circuit using these unconventional gates and to explore the potential advantages they bring to digital circuitry. Through detailed simulations and physical prototyping, we evaluate the performance of this innovative Full Adder design in terms of speed, power consumption, and scalability. Our findings suggest that the use of Peres, Fredkin, NOT, and Feynman gates in a Full Adder circuit can lead to more efficient and adaptable digital systems, paving the way for advancements in modern computing and signal processing technologies

Key Words

Reversible logic gate, Half adder, full adder

Cite This Article

"DESIGN AND IMPLEMENTATION OF HALF ADDER AND FULL ADDER USING REVERSIBLE LOGIC GATES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 1, page no.b523-b533, January-2024, Available :http://www.jetir.org/papers/JETIR2401160.pdf

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2349-5162 | Impact Factor 7.95 Calculate by Google Scholar

An International Scholarly Open Access Journal, Peer-Reviewed, Refereed Journal Impact Factor 7.95 Calculate by Google Scholar and Semantic Scholar | AI-Powered Research Tool, Multidisciplinary, Monthly, Multilanguage Journal Indexing in All Major Database & Metadata, Citation Generator

Cite This Article

"DESIGN AND IMPLEMENTATION OF HALF ADDER AND FULL ADDER USING REVERSIBLE LOGIC GATES", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 1, page no. ppb523-b533, January-2024, Available at : http://www.jetir.org/papers/JETIR2401160.pdf

Publication Details

Published Paper ID: JETIR2401160
Registration ID: 531142
Published In: Volume 11 | Issue 1 | Year January-2024
DOI (Digital Object Identifier): http://doi.one/10.1729/Journal.37461
Page No: b523-b533
Country: -, -, India .
Area: Engineering
ISSN Number: 2349-5162
Publisher: IJ Publication


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