• M.Sivaramaprasad
• P.Keerthi
• P. AdityaVardhan
• M. Amrutha
• Y.Mamillu

- A multiplier is an operation block found in every processing unit in major programs. Within the current framework, numerous multiplication algorithms have been developed. Designing the multiplier structure involves applying the Adder-based multiplication algorithm. Parallel prefix adders (PPAs) handle the last stage of addition for partial products in the current structure. Multiplier structures are implemented using the Kogge stone adder, Sklansky adder, Brent Kung adder, Ladner Fischer adder, and Han Carlson adder. A crucial factor in any application, such as multiplier design is operating speed. In the suggested method, a MAC unit is employed to increase the multiplier's speed. In the Xilinx 14.2 design suite, Verilog HDL is used to create all of the multiplier structures. The ISIM is used to mimic both the proposed and existing systems. The XST synthesizer is used to synthesize the proposed and existent structures, while the ISIM simulator is used for simulation. The suggested designs are examined in comparison to multiplier designs in terms of delay (ns) and number of LUTs.

Kogge stone adder (KSA), Adder based multiplier, Multiplier and Accumulator (MAC) Unit.

"FPGA BASED HIGH SPEED MULTIPLIER DESIGN USING KOGGE STONE ADDER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 4, page no.g747-g752, April-2024, Available :http://www.jetir.org/papers/JETIR2404695.pdf

"FPGA BASED HIGH SPEED MULTIPLIER DESIGN USING KOGGE STONE ADDER", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 4, page no. ppg747-g752, April-2024, Available at : http://www.jetir.org/papers/JETIR2404695.pdf