• Karthik Bandla
• Dhana Sri Darla
• Divya Teja Reddy Chekkera

Many signal processing and communication applications rely on complex floating point numbers as their main component. Hence, optimizing algorithms and hardware for complex number multiplication is a key focus to achieve faster processing and lower power consumption in these domains. Since multiplication speed directly impacts a system's overall performance. This study implements complex floating point multiplication utilizing array multiplier, Vedic multiplier, and CIFM multiplier using carry look ahead adder in Verilog on VIVADO DESIGN SUITE. The performance of these three multipliers mainly varies in parameters like delay, and power consumption. Based on the obtained outcomes, the best multiplier can be used for fast multiplication operations.

Vedic Multiplier, Urdhva Tiryagbhyam, Array Multiplier, Combined Integer Floating Point Multiplier

"Comparative Analysis of 32-Bit Complex Floating Point Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 4, page no.i108-i113, April-2024, Available :http://www.jetir.org/papers/JETIR2404815.pdf

"Comparative Analysis of 32-Bit Complex Floating Point Multiplier", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 4, page no. ppi108-i113, April-2024, Available at : http://www.jetir.org/papers/JETIR2404815.pdf