• A.S.N.Sambi Reddy
• Dr.D.Prabhakar
• B.Durga Prasad
• Ch.Sivani
• Ch.Rakesh

The relentless pursuit of performance optimization in processor design has led to the exploration of innovative methodologies and architectures. In this context, the utilization of Vedic Mathematics presents a promising avenue for enhancing the efficiency and performance of Reduced Instruction Set Computer (RISC) processors. Building upon the foundation laid by existing research, this paper proposes a novel extension to the design and verification of a 16-bit RISC processor, leveraging the principles of Vedic Mathematics. Reduced Instruction Set Computer (RISC) is a design which presents better performances, higher speed of operation and favors the smaller and simpler set of instructions. In addition to multiplier which is implemented using Vedic mathematics we are also proposing an adder which is hybrid adder for building higher bit adders in an area efficient which is implemented in addition as well as for compression in Vedic mathematic to obtain the output. A 16-bit RISC processor designed in this paper is capable of executing a greater number of instructions with simple design, using the Verilog Hardware Description Language (HDL) and the design is simulated in the Xilinx VIVADO design suite. The main achievement in this work is that the multiplier unit in Arithmetic and Logic Unit (ALU) and Multiplier and Accumulator (MAC) is implemented using Vedic Sutras. The main principle used in Vedic mathematics is to reduce the typical calculation of conventional mathematics to very simple one and hence reduce the overall computational complexity. In addition to these blocks, designed RISC Processor consists of other blocks like Control unit and data path, Register Bank, Program Counter and Memory. The proposed RISC processor is very simple and capable of executing 14 instructions. The achievement in this work is that savings in power in case of MAC and ALU is achieved compared to conventional ALU and MAC respectively. Also, the delay is reduced in MAC and ALU in comparison with conventional ALU and MAC correspondingly. These Vedic MAC and ALU are then integrated with other blocks in processor and 16-bit Vedic processor is developed. This reduces the delay and saves power compared to conventional processor. Hence the improvement in speed of operation, reduction in power utilization and less area utilization are the key features of designed RISC processor.

Reduced Instruction Set Computer; VonNeumann architecture; Verilog HDL, Vedic Mathematics, Urdhva-Tiryagbhyam Sutra

"Implementation and Validation of 16-Bit RISC Processor Using Vedic Mathematics", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 4, page no.k48-k52, April-2024, Available :http://www.jetir.org/papers/JETIR2404A09.pdf

"Implementation and Validation of 16-Bit RISC Processor Using Vedic Mathematics", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 4, page no. ppk48-k52, April-2024, Available at : http://www.jetir.org/papers/JETIR2404A09.pdf