• Sajal Agrawal
• Ashish Dubey

automated processes and autonomous systems are only possible because to the advancements in artificial intelligence (AI). The 6T-SRAM cell, which has a performance advantage over its competitors, is a promising option for use in AI hardware implementations. However, state-of-the-art AI hardware like NNs often accesses off-chip data, which slows down the whole system. These days, speed is of the essence for any electronic system, and eighty percent of all chips have some kind of memory. The size of memory chips, their speed, their leakage current, and their power efficiency have all decreased because to the widespread adoption of SRAM in numerous VLSI Chips. It has gained popularity as a data storage device because to its high storage density & fast access time. Recent rapid progress in low power & low voltage memory technology has prompted the research community to prioritise SRAM. The functionality and efficiency of SRAM & DRAM cells were examined. In this study, we present our work on enhancing the power efficiency of the 6T SRAM cell and its subsequent implementation.

CMOS, D-Flip Flop, Leakage Power, Delay, Cadence.

"Study and Analysis Resilient CMOS 6T SRAM using AI Application", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 4, page no.k264-k269, April-2024, Available :http://www.jetir.org/papers/JETIR2404A34.pdf

"Study and Analysis Resilient CMOS 6T SRAM using AI Application", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 4, page no. ppk264-k269, April-2024, Available at : http://www.jetir.org/papers/JETIR2404A34.pdf