• SAICHITR G B
• ASHWINI V

This paper is an outline of creating a multi AMBA system processor interface, which is designed to interconnect various AMBA processors. The main purpose of this interface is to simplify the connection between different AMBA AHB interfaces and external memory devices like RAM and REGISTER, using the high-performance features of the AMBA AHB. This research examines the use of Application Specific Integrated Circuits (ASICs) for integrating processors with functional units into System-On-Chip (SoC), which can run complex applications. It investigates how in ASIC environment processors communicate with their targets via standardized communication protocol across all targets. The paper also discusses problems connected with data throughput and inter-processor/RTL communication in present-day microprocessors and suggests that multiple AMBAs can be used simultaneously to have access to target components they are meant for. It further introduces a proposed arbitration system that manages multiprocessor access; and explores how bulk data access can be optimized while satisfying major ASIC design constraints like speed, low power consumption and efficient area utilization. In regard to these technologies, it was tested using simulation by verification using Verilog, which gave us remarkable outcomes.

AMBA AHB protocol; AMBA processor interface; multiprocessor arbitration; Verilog

"Multi-AMBA System Processor Interface for High- Performance SoC Integration", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 7, page no.g266-g271, July-2024, Available :http://www.jetir.org/papers/JETIR2407632.pdf

"Multi-AMBA System Processor Interface for High- Performance SoC Integration", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 7, page no. ppg266-g271, July-2024, Available at : http://www.jetir.org/papers/JETIR2407632.pdf