• Koilada Kalyani 2nd
• Rajani Alugonda 1st

A remarkably low-power Gray code counter(GCC) is proposed using 18T Hybrid Flipflop(HFF)[1]. Numbers are represented by bit sequences in the gray code, with only one bit separating each number from the next. To minimize the impact of clock overloading and lower the circuit's dynamic power consumption, the clock gating approach was used in its design. The entire design was built utilizing 45nm Cadence Virtuoso technology, and when compared to the standard positive edge triggered flipflop, there is a significant reduction in the dynamic power by at least 20%. The suggested circuit operates effectively at up to 1 GHz without error.

Hybrid flipflop, Low power VLSI, cadence virtuoso, clock Gating, Binary to gray conversion.

"Low power Clock Gated Gray Code Counter Using Hybrid Flipflop", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 9, page no.f304-f309, September-2024, Available :http://www.jetir.org/papers/JETIR2409565.pdf

"Low power Clock Gated Gray Code Counter Using Hybrid Flipflop", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 9, page no. ppf304-f309, September-2024, Available at : http://www.jetir.org/papers/JETIR2409565.pdf