• Yamini kuna
• Dr.U.V.Ratna Kumari
• Prasanthi Badugu

A parallel pipelined architecture is implemented for the transposition of a square matrix for a parallelism of eight. Parameters such as memory and latency are calculated for the parallel pipelined architecture. A controller manages the control strategy of a sequence of identical cascaded N path basic exchange circuits in the architecture, where N is the size of a N×N matrix. Verilog HDL is used to analyze WNS (Worst Negative Slack) values, total power consumption, total delay and resource utilization using Xilinx Vivado software. A parallel pipelined architecture for matrix transposition, addressing both square (8×8) and non-square matrices (9×6 and 8×4) is implemented with the parallelism that the respective matrix transposition architectures support and the effect of increasing parallelism on various parameters is observed

Parallel pipelining, square matrix transposition, hardware architecture, latency

"Parallel pipelined architecture for square matrix transposition with eight-way parallelism", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.11, Issue 11, page no.f368-f373, November-2024, Available :http://www.jetir.org/papers/JETIR2411540.pdf

"Parallel pipelined architecture for square matrix transposition with eight-way parallelism", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.11, Issue 11, page no. ppf368-f373, November-2024, Available at : http://www.jetir.org/papers/JETIR2411540.pdf