• Lakshmi Girish
• Keerthi M
• Priyadarshini N M
• Dr. Kiran Bailey

The Single-Cycle RISC-V Processor is an innovative microprocessor architecture that exemplifies efficiency and simplicity in design. This architecture is based on the RISC (Reduced Instruction Set Computing) principles, which prioritize a streamlined set of instructions, a consistent instruction length, and an increase in the number of general-purpose registers. These features facilitate faster execution of individual instructions and contribute to an overall simplified design. Operating under a load-store architecture, the Single-Cycle RISC-V Processor executes all instructions in a single clock cycle, making it particularly suitable for low-cost embedded devices. The design philosophy emphasizes minimalism and reduced complexity, resulting in a hardware structure that allows for enhanced pipelining and quicker execution times. The open-source nature of the RISC-V instruction set architecture (ISA) enables customization and adaptability across various computing applications. By implementing this architecture, the Single-Cycle RISC-V Processor represents a significant advancement in microprocessor technology. Its efficient execution model, combined with its scalability and flexibility, positions it as an ideal choice for modern computing systems, catering to the needs of both academic research and practical applications in diverse fields.

RISC-V (Reduced instruction set computer), Single cycle processor, Instruction Set Architecture (ISA), Data path, control unit.

"Single cycle RISC-V Processor", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 1, page no.e283-e288, January-2025, Available :http://www.jetir.org/papers/JETIR2501533.pdf

"Single cycle RISC-V Processor", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 1, page no. ppe283-e288, January-2025, Available at : http://www.jetir.org/papers/JETIR2501533.pdf