• K.Parvateesam
• K.Bhoomika
• P.N.V.S.S.K.Pavan
• M.Rohini

In this paper we are presenting an encryption algorithm called Advance Encryption Standard. We have designed AES algorithm using Verilog HDL and in this design we have used look up table substitution for byte in state matrix, also for low complexity and low latency hardware for efficient performance. This design was simulated in Xilinx ISE 14.7, compared results with previous design performances. The algorithm operates by first generating a random AES key, which is then used to encrypt the plaintext message. Subsequently, the AES key is encrypted using the recipient's public RSA key. The ciphertext (encrypted message) and the encrypted AES key are then transmitted. Upon reception, the recipient decrypts the AES key using their private RSA key. Finally, the decrypted AES key is used to decrypt the ciphertext, recovering the original plaintext. This hybrid approach leverages the speed of AES for data encryption and the security of RSA for key distribution.

Digital Communication, AES Algorithm, RSA Algorithm, Encryption, Decryption.

"A COMBINED MESSAGE ENCRYPTION AND DECRYPTION CRYPTOGRAPHIC ALGORITHM BASED ON AES AND RSA ALGORITHMS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 3, page no.f294-f301, March-2025, Available :http://www.jetir.org/papers/JETIR2503565.pdf

"A COMBINED MESSAGE ENCRYPTION AND DECRYPTION CRYPTOGRAPHIC ALGORITHM BASED ON AES AND RSA ALGORITHMS", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 3, page no. ppf294-f301, March-2025, Available at : http://www.jetir.org/papers/JETIR2503565.pdf