• Nisha Jatav
• Prof. Deepti Malviya

Cyclic Redundancy Check (CRC) is a widely used error detection technique in digital communication and data storage systems, relying on polynomial division over Finite Fields (Galois Fields, GF) for checksum generation. The implementation of CRC using Finite Field Multipliers (FFMs) on Field-Programmable Gate Arrays (FPGAs) enables high-speed computation with improved efficiency, making it suitable for real-time applications such as networking, wireless communication, and embedded systems. This paper reviews various VLSI-based architectures for CRC implementation, focusing on different multiplier designs, including serial, parallel, and hybrid approaches, along with optimization techniques such as pipeline processing, resource-sharing, and low-power methodologies.

CRC, Error, Correction, Speed, Power, Latency

"Review of Cyclic Redundancy Check Code for Finite Field Multiplier on FPGA", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 3, page no.h132-h135, March-2025, Available :http://www.jetir.org/papers/JETIR2503716.pdf

"Review of Cyclic Redundancy Check Code for Finite Field Multiplier on FPGA", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 3, page no. pph132-h135, March-2025, Available at : http://www.jetir.org/papers/JETIR2503716.pdf