• Dr.G.Jhansi Reddy
• Katkam Mamatha

This brief proposes a logic error detection circuit (LEDC)-equipped wide-range level shifter (LS) that uses less energy. A feedback pFET is incorporated into the suggested LS in order to address the static current, which is a drawback of the present mirror-based LS (CMLS). Similar to this, Wilson's CMLS (WCMLS) uses the feedback pFET to tackle the CMLS problem; however, because of the feedback pFET, it is unable to completely convert low supply voltage (VDDL) to high supply voltage (VDDH). On the other hand, the suggested LS can use the LEDC to convert VDDL to full VDDH. The post layout simulation was carried out using the 7- nm fin FET model in order to confirm the performance difference between the suggested LS and the previously suggested LS. The outcomes of the simulation of the suggested.Terms for the Index: Current mirror, level shifter (LS), low power, near-threshold operation, wide range.

Level Shifter, Voltage Range, Bidirectional Communication,MOSFET, Signal Integrity, Logic Error Detection.

"Wide - Range level shifter with logic error detection circuit for energy efficiency", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 3, page no.h193-h196, March-2025, Available :http://www.jetir.org/papers/JETIR2503723.pdf

"Wide - Range level shifter with logic error detection circuit for energy efficiency", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 3, page no. pph193-h196, March-2025, Available at : http://www.jetir.org/papers/JETIR2503723.pdf