• Dr. Jillella Venkateswara Rao
• Kongaru Laxmi Narasimha
• Chanumolu Sri Varsha
• Bandi Sai Komal
• Meka Manoj Reddy

This work presents the design of an automatic washing machine control system utilizing a Finite State Machine (FSM) implemented in Verilog. The FSM effectively models the washing process through distinct states: Check Door, Fill Water, Add Detergent, Cycle, Drain Water, and Spin. Each state is logically connected, ensuring smooth transitions based on real-time inputs such as water level, detergent presence, and task completion. A Verilog testbench simulates various scenarios to validate the FSM's functionality, confirming the system's reliability and operational efficiency. Utilizing EDA Playground for implementation and Aldec Riviera Pro 2023.04 for simulation, this work demonstrates the practical application of FSMs in automating washing machines. The results highlight the system's safety, efficiency, and user-friendliness, establishing a solid foundation for future advancements in smart appliance technology.

Automatic Washing Machine Control System, FSM, Verilog, Check Door, Fill Water, Add Detergent, Cycle, Drain Water, Spin, Eda Playground, Aldec Riviera Pro.

"Implemenation of Automatic Washing Machine Control System using Verilog HDL", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 3, page no.j433-j436, March-2025, Available :http://www.jetir.org/papers/JETIR2503956.pdf

"Implemenation of Automatic Washing Machine Control System using Verilog HDL", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 3, page no. ppj433-j436, March-2025, Available at : http://www.jetir.org/papers/JETIR2503956.pdf