• V. Rohini
• N. Srinivasulu
• K. Betty Surya
• V. Sreelekha
• Sk.Arif

An eighteen transistor true 1 clocking flip-flop with very little power is proposed in this brief. A single-bit synchronous bistable element, the flip-flop stores information. To design this Master Slave (MS) type architecture, topological, logical, and adaptive coupling techniques are employed. The above methods, which include complementary pass transistor logic and static complementary MOS logic, are used to keep the minimum number of transistors. It also offers low power, a low delay that speeds up the flip-flops, and low complexity by reducing the transistor count. Cadence Virtuoso is used to build the proposed circuit, which is then compared to the five other flip-flop-based logic structures that have been reported. The proposed hybrid logic architecture has showed the highest percentage, i.e., 49.73% improvement in terms of power as compared to LRFF. It also improved the delay and energy efficiency (EDP). 20K samples were used in the C to Q Delay Monte Carlo simulation. By reducing the number of PMOS transistors, the total area of the proposed flip-flop reduces by a minimum of 9.49% in comparison to state of the art work. The proposed circuit can work properly within a frequency range upto 1 GHz. It is also compared with reported 18T TSPC flip-flop.

A PARTIALLY STATIC HIGH FREQUENCY 18T HYBRID TOPOLOGICAL FLIP-FLOP DESIGN FOR LOW POWER APPLICATION

"A PARTIALLY STATIC HIGH FREQUENCY 18T HYBRID TOPOLOGICAL FLIP-FLOP DESIGN FOR LOW POWER APPLICATION", International Journal of Emerging Technologies and Innovative Research (www.jetir.org), ISSN:2349-5162, Vol.12, Issue 4, page no.n544-n549, April-2025, Available :http://www.jetir.org/papers/JETIR2504D64.pdf

"A PARTIALLY STATIC HIGH FREQUENCY 18T HYBRID TOPOLOGICAL FLIP-FLOP DESIGN FOR LOW POWER APPLICATION", International Journal of Emerging Technologies and Innovative Research (www.jetir.org | UGC and issn Approved), ISSN:2349-5162, Vol.12, Issue 4, page no. ppn544-n549, April-2025, Available at : http://www.jetir.org/papers/JETIR2504D64.pdf